1. Field of the Invention
The present invention pertains to the field of computer systems having multiple processors. More particularly, this invention relates to the field of initializing processors to operate independently or as master/checker pairs.
2. Background
In modern computer systems, multiple processing agents are often coupled to a bus. These multiple processing agents frequently operate in parallel, i.e., multiple processor (MP) mode. In MP mode, each agent performs a different set of tasks to process the software running on the system. Thus, each agent operates independently; that is, each agent is performing a different set of tasks, although these tasks may be combined with the tasks performed by another processor in order to increase the execution speed of the software.
Occasionally, however, it may be beneficial for a computer system to operate such that one processing agent checks the operation of another processing agent. In such a situation, each pair of processing agents may thus create a functional redundancy checking (FRC) master/checker pair. That is, one processing agent, the master agent, operates independently as described above. A second processing agent, the checker agent, performs the same tasks in lock-step as the master agent. Thus, the checker agent operates as if it were the master agent. The results of the tasks performed by the checker agent are checked against those of the master agent; if the calculations do not match then a FRC error results.
As technology advances, the processing agents used in computer systems become more and more reliable. Thus, for the majority of applications and uses the MP mode operates within an acceptable margin of error. However, in some situations, such as certain military or high-risk applications, the use of the FRC-master/checker mode would be beneficial.
Thus, it would be beneficial for a processing agent to be able to efficiently operate independently, however also have the capability to operate as an agent within an FRC-master/checker pair. Furthermore, it would be beneficial for a processing agent to operate in FRC mode with a minimal amount of complexity and overhead due to the infrequent use of the FRC mode. The present invention provides such a solution.
FIG. 1 shows a block diagram of a prior art configuration for a FRC-master/checker pair. A processor 100 is shown with multiple output signals 106, 108, and 110, and corresponding input signals 105, 107 and 109, respectively. The output signals originate within the internal processor logic 112 and are run through FRC logic 115 before being output to the bus. In the output mode, an output signal 106 from processor 100 drives exclusive-or (XOR) gate 135 and three-state buffer 120; when processor 100 is a FRC master, buffer 120 is enabled. Signal 125 is the output of buffer 120, which directly drives the bus pin 126 and buffer 130. When processor 100 receives input from bus pin 126, signal 125 is fed back as an input to buffer 130. Signal 105, the output of buffer 130, is fed back to processor logic 112.
Signal 105 is also fed as a second input to XOR gate 135. Thus, the two inputs to XOR gate 135 are always at the same logic level when processor 100 is driving the output. When the processor is a bus master, XOR gate 135 is disabled.
Exclusive-or gate 135 is enabled if processor 100 is operating as a FRC checker. When processor 100 is a checker processor, buffer 120 is disabled. That is, all output signals from processor logic 112, such as output signal 106, reach a buffer, such as buffer 120, and terminate. Thus, the outputs from processor 100 will never be driving the bus. Instead, the corresponding output from the master processor travels over the bus and onto bus pin 126, which is received by the checker as signal 125. Since the checker processor 100 and the master processor are performing the same set of tasks, this signal from the master processor should be at the same level as checker processor 100 is issuing on output signal 106.
If these two signals are the same, then the output of XOR gate 135 is low, which indicates to the FRC error logic that no error occurred. However, if the two inputs are not the same, then the output of XOR gate 135 is high, which indicates to the FRC error logic that an error occurred. An error must have occurred because the output from the checker processor, processor 100, does not match the corresponding output from the master processor. Thus, the FRC error logic is informed of an error and may respond accordingly.
In many modern computer system applications, one primary goal is support for a MP-ready system. A secondary goal is to allow a MP-ready system to be reconfigurable to a FRC system with a simple configuration option. Thus, a MP-ready system containing "2n" processors should be capable of reconfiguration to a FRC system of "n" FRC master/checker pairs. Such a system allows a system manufacturer to build a common processor board accommodating both configurations and choose the mode of operation by changing the simple configuration option.
One important pre-requisite of the prior art systems, such as that shown in FIG. 1, was that the master and checker processors had their identical pins tied together. This ensured that the checker processor checked all the corresponding outputs of the master processor.
One problem in modern multiple processor computer systems, however, is that the interconnection of signals between processing agents may vary. That is, the output signal from the master processor is not necessarily tied to the same pin of the checker processor. Thus, in such a computer system the FRC configuration of the prior art would not produce the correct results. Therefore, in such a computer system it would be beneficial to provide a system which supports FRC mode with minimal complexity while at the same time allows efficient operation in multiple processor mode. Additionally, it would be beneficial to provide a versatile system which allows for processor interchangability with minimal overhead. The present invention provides such a system.